下述代码描述的状态机结构定义了几个状态？ARCHITECTURE behv OF FSM_EXP ISTYPE FSM_ST IS (s0, s1, s2, s3, S4);SIGNAL c_st, next_state: FSM_ST;-BEGINREG: PROCESS (reset,clk) BEGINIF reset='0' THEN c_st<=s0;ELSIF clk='1' AND clk'EVENT THEN c_st <= next_state; END IF;END PROCESS REG;COM:PROCESS(c_st, state_inputs) BEGINCASE c_st ISWHEN s0 => comb_outputs<= 5;IF state_inputs="00" THEN next_state<=s0;ELSE next_state<=s1; END IF;WHEN s1 => comb_outputs<= 8;IF state_inputs="01" THEN next_state<=s1;ELSE next_state<=s2; END IF;WHEN s2 => comb_outputs<= 12;IF state_inputs="10" THEN next_state <= s0;ELSE next_state <= s3; END IF;WHEN s3 => comb_outputs <= 14;IF state_inputs="11" THEN next_state <= s3;ELSE next_state<=s4; END IF;WHEN s4 => comb_outputs <= 9; next_state <= s0;WHEN OTHERS => next_state <= s0 ;END case;END PROCESS COM;END behv;
下述代码描述的状态机结构定义了几个状态？
ARCHITECTURE behv OF FSM_EXP IS
TYPE FSM_ST IS (s0, s1, s2, s3, S4);
SIGNAL c_st, next_state: FSM_ST;-
BEGIN
REG: PROCESS (reset,clk) BEGIN
IF reset='0' THEN c_st<=s0;
ELSIF clk='1' AND clk'EVENT THEN c_st <= next_state; END IF;
END PROCESS REG;
COM:PROCESS(c_st, state_inputs) BEGIN
CASE c_st IS
WHEN s0 => comb_outputs<= 5;
IF state_inputs="00" THEN next_state<=s0;
ELSE next_state<=s1; END IF;
WHEN s1 => comb_outputs<= 8;
IF state_inputs="01" THEN next_state<=s1;
ELSE next_state<=s2; END IF;
WHEN s2 => comb_outputs<= 12;
IF state_inputs="10" THEN next_state <= s0;
ELSE next_state <= s3; END IF;
WHEN s3 => comb_outputs <= 14;
IF state_inputs="11" THEN next_state <= s3;
ELSE next_state<=s4; END IF;
WHEN s4 => comb_outputs <= 9; next_state <= s0;
WHEN OTHERS => next_state <= s0 ;
END case;
END PROCESS COM;
END behv;
题目解答
答案
解析
本题考查对VHDL代码中状态机状态数量的识别。解题思路是在代码中找到定义状态的数据类型，统计其中所包含的状态数量。
- 首先，在代码中找到定义状态的数据类型声明语句：
- 代码里有
TYPE FSM_ST IS (s0, s1, s2, s3, S4);这一语句，它定义了一个名为FSM_ST的数据类型，此数据类型包含了多个状态。
- 代码里有
- 接着，对该数据类型中包含的状态进行计数：
- 可以清晰看到，
FSM_ST类型里包含了s0、s1、s2、s3和S4这5个状态。
- 可以清晰看到，
- 最后，确认代码中对这些状态的处理情况：
- 在
CASE语句中，对s0、s1、s2、s3和S4这5个状态都进行了相应的处理，并且通过WHEN OTHERS确保了未定义状态会回归到s0，这进一步说明了这5个状态是有效的。
- 在